In recent years, large scale computer systems having multistage crossbar switches have been introduced. The crossbar switches mentioned here form, in a dynamic manner, paths that connect, one to one, each unit, such as a central processing unit, a memory unit, and an input-output device, that is installed in a computer. Packets that are transmitted/received between each unit are transferred, using paths formed by the multistage crossbar switches, between the crossbar switches.
As illustrated in FIG. 10, chips included in crossbar switches each store, in storage spaces (i.e., history, random access memory (RAM), or the like), historical information (hereinafter, referred to as a “log”). Accordingly, when a system operator checks the performance or the design validity of a crossbar switch system, the historical information is collected for each chip and analyzed. The arrow illustrated in FIG. 10 indicates an example of a path taken when a packet is sent from an “I/O (i.e., Input/Output or input-output device)” to an “SB (i.e., system board, central processing unit, or the like)”. As illustrated in FIG. 10, the log information on the packet is collected for each chip, such as information collected at point A, information collected at point B, information collected at point D, and information collected at point F. In FIG. 10, letters of the alphabet after the “packet” do not indicate a collection location but indicate that the information collected for each chip is fragmentary information of various kinds.
Japanese Laid-open Patent Publication No. 2003-324478 discloses a technology for collecting, in a system that includes multiple information processing apparatuses, log information on the information processing apparatuses for each information processing apparatus. Furthermore, Japanese Laid-open Patent Publication No. 11-355276 discloses a technology in which, in a system in which multiple computers are connected via a network, diagnostic packets containing path-route information are created and sent to the network.
However, with the conventional technologies, there is a problem in that it is difficult to analyze packets that are forwarded between the crossbar switches. In other words, because the log information collected for each chip cannot be anything but fragmented, it is difficult to analyze packets by focusing on the behavior of the packets that are forwarded between the crossbar switches. Furthermore, in a large scale system that includes multistage crossbar switches, it is difficult to check the performance or design validity of the entire system only by using performance information or event information that is collected for each chip. Furthermore, the technologies disclosed in the above-described Japanese Laid-open Patent Publication No. 2003-324478 and Japanese Laid-open Patent Publication No. 11-355276 cannot solve the above problem.